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RM0008
Figure 22. DMA block diagram in connectivity line devices
ICode
DMA controller (DMA)
DCode
FLITF
Flash
Cortex-M3
Sys tem
SRAM
DMA1
Ch.1
Ch.2
Ch.7
DMA
Reset & clock
control (RCC)
Bridge 2
Bridge 1
APB1
APB2
Arbiter
RTC
AHB Slave
DMA request
ADC1
ADC2
USART1
SPI1
TIM1
GPIOC
GPIOD
GPIOE
EXTI
AFIO
DAC SPI3/I2S
PWR SPI2/I2S
BKP IWDG
CAN1 WWDG
CAN2
DMA2
Ch.1
Ch.2
DMA request
GPIOA
GPIOB
I2C2
I2C1
UART5
UART4
TIM7
TIM6
TIM5
TIM4
USART3 TIM3
Ch.5
USART2 TIM2
Arbiter
AHB Slave
Ethernet MAC
USB OTG FS
ai15811
1. The DMA2 controller is available only in high-density and connectifity line devices.
2. SPI/I2S3, UART4, TIM5, TIM6, TIM7 and DAC DMA requests are available only in high-density and
connectivity line devices.
3. ADC3, SDIO and TIM8 DMA requests are available only in high-density devices.
10.3
10.3.1
DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex?-M3 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
Doc ID 13902 Rev 9
183/995
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